Frequency synthesizers utilized in known radio frequency (RF) communication devices, such as a RF transmitter, have included a voltage controlled oscillator and a reference oscillator coupled together in a phase locked loop. A voltage-controlled oscillator or VCO is an electronic oscillator designed to be controlled in oscillation frequency by a voltage supplied to a control input. The frequency of oscillation fVCO depends on the applied DC voltage. The VCO frequency is divided by a 1/N divider to a frequency comparable to a reference frequency fref. A phase detector PD compares the phase of the reference frequency with the phase of the divided VCO frequency out of the 1/N divider. A phase difference will result in a phase error signal on the output of the phase detector. Usually this error signal is either a positive or negative current pulse with a duration equal to the difference in phase, wherein the direction of the current depends on the direction of the error. The translation of the phase error into a current is performed inside the phase detector PD. This translation is done with a charge pump, named so as to indicate that charge is pumped into the loop filter. The loop filter low-pass filters the current representing the phase error so as to obtain an averaged phase error which is fed back to the control input of the VCO. The loop is a negative feedback loop. If the VCO frequency drifts, the error signal will increase/decrease driving the VCO frequency in the opposite direction so as to reduce the error. Thus, the VCO output is locked to the reference frequency at the other input of the phase detector PD.
Practical design aspects concern the amount of time the frequency synthesizer can switch from channel to channel, time to lock when first switched on, and how much noise there is in the VCO output. All of these are a function of the loop filter of the system, which usually is a low-pass filter placed between the output of the phase comparator and the input of the VCO. Usually the output of a phase comparator is in the form of short error pulses, but the input of the VCO must be a smooth noise-free DC voltage. Any noise on this signal naturally causes frequency modulation of the VCO. Heavy filtering will make the VCO slow to respond to changes, causing drift and slow response time, but light filtering will produce noise and other problems with harmonics. Thus, the design of the filter is critical to the performance of the system. U.S. Pat. No. 6,614,869B2 discloses a PLL-based frequency synthesizer. The output of the VCO is sampled with a sampling frequency which is substantially less than the frequency of the VCO signal. However, sampling introduces quantization and phase noise in the loop which is still found at the input of the VCO resulting in a VCO output signal with a frequency which generally is not stable enough for use in transceivers.
U.S. Pat. No. 7,279,988B1 discloses a digital frequency locked loop and phase locked loop frequency synthesizer. In a first state, the frequency and phase locked loop operates in the frequency locked loop (FLL) mode for initial frequency acquisition. Once the frequency and phase locked loop has locked in FLL mode, the frequency and phase locked loop transitions to the phase locked loop (PLL) mode for normal operation. The synthesizer includes a Digitally Controlled Oscillator (DCO) and a 2M counter which operates at the output frequency of the DCO. These components are rather power-consuming.
It is commonly known that sub-sampling enables to reduce the power consumption but it introduces quantization noise. When sub-sampling is used in a PLL, this quantization noise feeds through the phase frequency detector (PFD), is filtered by the loop filter and then presented at the control input of the VCO. The signal generated by the VCO will have a noisy frequency as it includes the quantization noise. In most cases, the loop filter of a PLL has an out-of-band attenuation with a roll-off of 6 dB per octave. In order to fulfill stability criteria, a PLL allows limited filtering, the filtering is part of the loop and the loop filter of a PLL can, in most cases, for higher frequencies, be considered as a first order filter. The quantization noise at the input can be reduced by decreasing the loop-bandwidth. However, this will increase the settling time of the transceiver.
Frequency synthesizers can also be built using a Frequency Locked Loop (FLL). Generally, this is not done, mostly because there are noise disadvantages for example with respect to the in-band phase noise. The characteristics of a PLL for use in a transceiver are regarded to be superior over the characteristics of a FLL. Practical aspects of a frequency synthesizer concern the amount of time during which the system can switch from channel to channel, time to lock when first switched on, and how much noise there is in the output. All of these are influenced by the loop filter of the system, which is a low-pass filter placed between the output of the frequency comparator and the input of the VCO. Usually the output of a frequency comparator is in the form of short error pulses, but the input of the VCO must be a smooth noise-free DC voltage. (Any noise on this signal naturally causes frequency modulation of the VCO.).
A filter with a lower cut-off frequency will make the VCO slower to respond on changes and will give it less control over low frequency phase noise out produced inside the VCO, but a higher cut-off frequency will let pass more noise out of the phase or frequency comparator. Thus, the design of the filter is critical for the performance of the system.